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-- Company: BASH Robotics
-- Engineer: Will Rozzo
-- 
-- Create Date:    15:09:03 07/18/2009 
-- Design Name: 
-- Module Name:    OpMem_Poller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

-- After thinking about it, we might not need this necessarily. We might be able to just pipe the data straight to the next component
-- We will keep this for now because it can hold data based on a state that can be used in the next state or something
entity OpMem_Poller is

Port ( 	   currState : in STD_LOGIC_VECTOR( 1 downto 0 ); -- I think we are cool with 4 states for now, can add more later
				clk : in STD_LOGIC;
				rst : in STD_LOGIC;
				inPkt : in  STD_LOGIC_VECTOR(31 downto 0 ); -- Data gathered from Op memory
				outPkt : out STD_LOGIC_VECTOR(31 downto 0)); -- Data sending to I2C Data Handler
				
end OpMem_Poller;

architecture Behavioral of OpMem_Poller is

signal pollerData : STD_LOGIC_VECTOR(31 downto 0);

begin

	process( clk, inPkt, currState, rst) is
	begin
		if( rising_edge(clk) and currState = "01" ) then  -- hard coded the state in, I have not determined what
																			  -- happens on each state yet or if we need more states
			pollerData <= inPkt;	

			if( rst = '1' ) then
				pollerData <= "00000000000000000000000000000000";
			end if;
	
		end if;
		

		outPkt <= pollerData; --will always output its data on the clock

	end process;
	


end Behavioral;

